2018-02-17 22:06:11 +01:00
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using ChocolArm64.Decoder;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection.Emit;
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Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
* Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics, some CQ improvements
* Remove useless space
* Address PR feedback
* Revert EmitVectorZero32_128 changes
2018-09-27 04:30:21 +02:00
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using System.Runtime.Intrinsics;
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using System.Runtime.Intrinsics.X86;
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2018-02-17 22:06:11 +01:00
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using static ChocolArm64.Instruction.AInstEmitSimdHelper;
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namespace ChocolArm64.Instruction
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{
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static partial class AInstEmit
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{
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public static void Fcvt_S(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
* Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics, some CQ improvements
* Remove useless space
* Address PR feedback
* Revert EmitVectorZero32_128 changes
2018-09-27 04:30:21 +02:00
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if (AOptimizations.UseSse2)
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{
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if (Op.Size == 1 && Op.Opc == 0)
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{
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//Double -> Single.
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AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorSingleZero));
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2018-02-17 22:06:11 +01:00
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Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
* Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics, some CQ improvements
* Remove useless space
* Address PR feedback
* Revert EmitVectorZero32_128 changes
2018-09-27 04:30:21 +02:00
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EmitLdvecWithCastToDouble(Context, Op.Rn);
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2018-02-17 22:06:11 +01:00
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Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
* Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics, some CQ improvements
* Remove useless space
* Address PR feedback
* Revert EmitVectorZero32_128 changes
2018-09-27 04:30:21 +02:00
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Type[] Types = new Type[] { typeof(Vector128<float>), typeof(Vector128<double>) };
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ConvertScalarToVector128Single), Types));
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Context.EmitStvec(Op.Rd);
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}
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else if (Op.Size == 0 && Op.Opc == 1)
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{
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//Single -> Double.
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AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorDoubleZero));
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Context.EmitLdvec(Op.Rn);
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Type[] Types = new Type[] { typeof(Vector128<double>), typeof(Vector128<float>) };
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ConvertScalarToVector128Double), Types));
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EmitStvecWithCastFromDouble(Context, Op.Rd);
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}
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else
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{
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//Invalid encoding.
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throw new InvalidOperationException();
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}
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}
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else
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{
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EmitVectorExtractF(Context, Op.Rn, 0, Op.Size);
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EmitFloatCast(Context, Op.Opc);
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EmitScalarSetF(Context, Op.Rd, Op.Opc);
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}
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2018-02-17 22:06:11 +01:00
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}
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2018-02-17 22:59:37 +01:00
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public static void Fcvtas_Gp(AILEmitterCtx Context)
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{
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2018-02-24 01:59:38 +01:00
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EmitFcvt_s_Gp(Context, () => EmitRoundMathCall(Context, MidpointRounding.AwayFromZero));
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2018-02-17 22:59:37 +01:00
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}
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public static void Fcvtau_Gp(AILEmitterCtx Context)
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{
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2018-02-24 01:59:38 +01:00
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EmitFcvt_u_Gp(Context, () => EmitRoundMathCall(Context, MidpointRounding.AwayFromZero));
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2018-02-17 22:59:37 +01:00
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}
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2018-03-05 16:58:19 +01:00
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public static void Fcvtl_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int SizeF = Op.Size & 1;
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int Elems = 4 >> SizeF;
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2018-10-23 16:12:45 +02:00
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int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
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2018-03-05 16:58:19 +01:00
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for (int Index = 0; Index < Elems; Index++)
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{
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if (SizeF == 0)
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{
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2018-07-12 20:51:02 +02:00
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EmitVectorExtractZx(Context, Op.Rn, Part + Index, 1);
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Context.Emit(OpCodes.Conv_U2);
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2018-10-23 16:12:45 +02:00
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Context.EmitLdarg(ATranslatedSub.StateArgIdx);
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Context.EmitCall(typeof(ASoftFloat16_32), nameof(ASoftFloat16_32.FPConvert));
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2018-03-05 16:58:19 +01:00
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}
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else /* if (SizeF == 1) */
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{
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EmitVectorExtractF(Context, Op.Rn, Part + Index, 0);
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Context.Emit(OpCodes.Conv_R8);
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}
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2018-10-23 16:12:45 +02:00
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EmitVectorInsertTmpF(Context, Index, SizeF);
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2018-03-05 16:58:19 +01:00
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}
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2018-10-23 16:12:45 +02:00
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Context.EmitLdvectmp();
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Context.EmitStvec(Op.Rd);
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2018-03-05 16:58:19 +01:00
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}
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2018-02-17 22:06:11 +01:00
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public static void Fcvtms_Gp(AILEmitterCtx Context)
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{
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2018-02-24 01:59:38 +01:00
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EmitFcvt_s_Gp(Context, () => EmitUnaryMathCall(Context, nameof(Math.Floor)));
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}
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public static void Fcvtmu_Gp(AILEmitterCtx Context)
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{
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EmitFcvt_u_Gp(Context, () => EmitUnaryMathCall(Context, nameof(Math.Floor)));
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2018-02-17 22:06:11 +01:00
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}
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2018-03-05 16:58:19 +01:00
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public static void Fcvtn_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int SizeF = Op.Size & 1;
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int Elems = 4 >> SizeF;
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2018-10-23 16:12:45 +02:00
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int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
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if (Part != 0)
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{
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Context.EmitLdvec(Op.Rd);
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Context.EmitStvectmp();
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}
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2018-03-05 16:58:19 +01:00
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for (int Index = 0; Index < Elems; Index++)
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{
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2018-10-23 16:12:45 +02:00
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EmitVectorExtractF(Context, Op.Rn, Index, SizeF);
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2018-03-05 16:58:19 +01:00
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if (SizeF == 0)
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{
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2018-10-23 16:12:45 +02:00
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Context.EmitLdarg(ATranslatedSub.StateArgIdx);
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Context.EmitCall(typeof(ASoftFloat32_16), nameof(ASoftFloat32_16.FPConvert));
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Context.Emit(OpCodes.Conv_U8);
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EmitVectorInsertTmp(Context, Part + Index, 1);
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2018-03-05 16:58:19 +01:00
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}
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else /* if (SizeF == 1) */
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{
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Context.Emit(OpCodes.Conv_R4);
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2018-10-23 16:12:45 +02:00
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EmitVectorInsertTmpF(Context, Part + Index, 0);
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2018-03-05 16:58:19 +01:00
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}
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}
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2018-03-05 20:18:37 +01:00
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2018-10-23 16:12:45 +02:00
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Context.EmitLdvectmp();
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Context.EmitStvec(Op.Rd);
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if (Part == 0)
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2018-03-05 20:18:37 +01:00
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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2018-03-05 16:58:19 +01:00
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}
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Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, Umlsl_V, Saddl_V, Ssubl_V, Usubl_V instructions; add 8 FP & 16 S/Umlal_V, S/Umlsl_V, S/Uaddl_V, S/Usubl_V Tests. (#390)
* Update AOpCodeTable.cs
* Update AInstEmitSimdCvt.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update Instructions.cs
* Update CpuTestSimdReg.cs
* Update CpuTestSimd.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update Instructions.cs
* Update CpuTestSimdReg.cs
* Add QCFlagBit.
* Add QCFlagBit.
2018-09-01 16:52:51 +02:00
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public static void Fcvtns_S(AILEmitterCtx Context)
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{
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EmitFcvtn(Context, Signed: true, Scalar: true);
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}
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public static void Fcvtns_V(AILEmitterCtx Context)
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{
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EmitFcvtn(Context, Signed: true, Scalar: false);
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}
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public static void Fcvtnu_S(AILEmitterCtx Context)
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{
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EmitFcvtn(Context, Signed: false, Scalar: true);
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}
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public static void Fcvtnu_V(AILEmitterCtx Context)
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{
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EmitFcvtn(Context, Signed: false, Scalar: false);
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}
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2018-02-17 22:06:11 +01:00
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public static void Fcvtps_Gp(AILEmitterCtx Context)
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{
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2018-02-24 01:59:38 +01:00
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EmitFcvt_s_Gp(Context, () => EmitUnaryMathCall(Context, nameof(Math.Ceiling)));
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}
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public static void Fcvtpu_Gp(AILEmitterCtx Context)
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{
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EmitFcvt_u_Gp(Context, () => EmitUnaryMathCall(Context, nameof(Math.Ceiling)));
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2018-02-17 22:06:11 +01:00
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}
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public static void Fcvtzs_Gp(AILEmitterCtx Context)
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{
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2018-02-24 01:59:38 +01:00
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EmitFcvt_s_Gp(Context, () => { });
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2018-02-17 22:06:11 +01:00
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}
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public static void Fcvtzs_Gp_Fix(AILEmitterCtx Context)
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{
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2018-02-24 01:59:38 +01:00
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EmitFcvtzs_Gp_Fix(Context);
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2018-02-17 22:06:11 +01:00
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}
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2018-05-18 19:44:49 +02:00
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public static void Fcvtzs_S(AILEmitterCtx Context)
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{
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EmitScalarFcvtzs(Context);
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}
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2018-02-17 22:06:11 +01:00
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public static void Fcvtzs_V(AILEmitterCtx Context)
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{
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2018-02-24 01:59:38 +01:00
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EmitVectorFcvtzs(Context);
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2018-02-17 22:06:11 +01:00
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}
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public static void Fcvtzu_Gp(AILEmitterCtx Context)
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{
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2018-02-24 01:59:38 +01:00
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EmitFcvt_u_Gp(Context, () => { });
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2018-02-17 22:06:11 +01:00
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}
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public static void Fcvtzu_Gp_Fix(AILEmitterCtx Context)
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{
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2018-02-24 01:59:38 +01:00
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EmitFcvtzu_Gp_Fix(Context);
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2018-02-17 22:06:11 +01:00
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}
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2018-05-18 19:44:49 +02:00
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public static void Fcvtzu_S(AILEmitterCtx Context)
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{
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EmitScalarFcvtzu(Context);
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}
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2018-02-17 22:06:11 +01:00
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public static void Fcvtzu_V(AILEmitterCtx Context)
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{
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2018-02-24 01:59:38 +01:00
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EmitVectorFcvtzu(Context);
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2018-02-17 22:06:11 +01:00
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}
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public static void Scvtf_Gp(AILEmitterCtx Context)
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{
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AOpCodeSimdCvt Op = (AOpCodeSimdCvt)Context.CurrOp;
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Context.EmitLdintzr(Op.Rn);
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if (Context.CurrOp.RegisterSize == ARegisterSize.Int32)
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{
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Context.Emit(OpCodes.Conv_U4);
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}
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EmitFloatCast(Context, Op.Size);
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EmitScalarSetF(Context, Op.Rd, Op.Size);
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}
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public static void Scvtf_S(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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2018-02-20 18:39:03 +01:00
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EmitVectorExtractSx(Context, Op.Rn, 0, Op.Size + 2);
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2018-02-17 22:06:11 +01:00
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EmitFloatCast(Context, Op.Size);
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EmitScalarSetF(Context, Op.Rd, Op.Size);
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}
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public static void Scvtf_V(AILEmitterCtx Context)
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{
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EmitVectorCvtf(Context, Signed: true);
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}
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public static void Ucvtf_Gp(AILEmitterCtx Context)
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{
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AOpCodeSimdCvt Op = (AOpCodeSimdCvt)Context.CurrOp;
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Context.EmitLdintzr(Op.Rn);
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if (Context.CurrOp.RegisterSize == ARegisterSize.Int32)
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{
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Context.Emit(OpCodes.Conv_U4);
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}
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Context.Emit(OpCodes.Conv_R_Un);
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EmitFloatCast(Context, Op.Size);
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EmitScalarSetF(Context, Op.Rd, Op.Size);
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}
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public static void Ucvtf_S(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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EmitVectorExtractZx(Context, Op.Rn, 0, Op.Size + 2);
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Context.Emit(OpCodes.Conv_R_Un);
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EmitFloatCast(Context, Op.Size);
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EmitScalarSetF(Context, Op.Rd, Op.Size);
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}
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public static void Ucvtf_V(AILEmitterCtx Context)
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{
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EmitVectorCvtf(Context, Signed: false);
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}
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private static int GetFBits(AILEmitterCtx Context)
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{
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if (Context.CurrOp is AOpCodeSimdShImm Op)
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{
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|
|
return GetImmShr(Op);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitFloatCast(AILEmitterCtx Context, int Size)
|
|
|
|
{
|
|
|
|
if (Size == 0)
|
|
|
|
{
|
|
|
|
Context.Emit(OpCodes.Conv_R4);
|
|
|
|
}
|
|
|
|
else if (Size == 1)
|
|
|
|
{
|
|
|
|
Context.Emit(OpCodes.Conv_R8);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
throw new ArgumentOutOfRangeException(nameof(Size));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, Umlsl_V, Saddl_V, Ssubl_V, Usubl_V instructions; add 8 FP & 16 S/Umlal_V, S/Umlsl_V, S/Uaddl_V, S/Usubl_V Tests. (#390)
* Update AOpCodeTable.cs
* Update AInstEmitSimdCvt.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update Instructions.cs
* Update CpuTestSimdReg.cs
* Update CpuTestSimd.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update Instructions.cs
* Update CpuTestSimdReg.cs
* Add QCFlagBit.
* Add QCFlagBit.
2018-09-01 16:52:51 +02:00
|
|
|
private static void EmitFcvtn(AILEmitterCtx Context, bool Signed, bool Scalar)
|
|
|
|
{
|
|
|
|
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
|
|
|
|
|
|
|
int SizeF = Op.Size & 1;
|
|
|
|
int SizeI = SizeF + 2;
|
|
|
|
|
|
|
|
int Bytes = Op.GetBitsCount() >> 3;
|
|
|
|
int Elems = !Scalar ? Bytes >> SizeI : 1;
|
|
|
|
|
|
|
|
if (Scalar && (SizeF == 0))
|
|
|
|
{
|
|
|
|
EmitVectorZeroLowerTmp(Context);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (int Index = 0; Index < Elems; Index++)
|
|
|
|
{
|
|
|
|
EmitVectorExtractF(Context, Op.Rn, Index, SizeF);
|
|
|
|
|
|
|
|
EmitRoundMathCall(Context, MidpointRounding.ToEven);
|
|
|
|
|
|
|
|
if (SizeF == 0)
|
|
|
|
{
|
|
|
|
AVectorHelper.EmitCall(Context, Signed
|
|
|
|
? nameof(AVectorHelper.SatF32ToS32)
|
|
|
|
: nameof(AVectorHelper.SatF32ToU32));
|
|
|
|
|
|
|
|
Context.Emit(OpCodes.Conv_U8);
|
|
|
|
}
|
|
|
|
else /* if (SizeF == 1) */
|
|
|
|
{
|
|
|
|
AVectorHelper.EmitCall(Context, Signed
|
|
|
|
? nameof(AVectorHelper.SatF64ToS64)
|
|
|
|
: nameof(AVectorHelper.SatF64ToU64));
|
|
|
|
}
|
|
|
|
|
|
|
|
EmitVectorInsertTmp(Context, Index, SizeI);
|
|
|
|
}
|
|
|
|
|
|
|
|
Context.EmitLdvectmp();
|
|
|
|
Context.EmitStvec(Op.Rd);
|
|
|
|
|
|
|
|
if ((Op.RegisterSize == ARegisterSize.SIMD64) || Scalar)
|
|
|
|
{
|
|
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-02-24 01:59:38 +01:00
|
|
|
private static void EmitFcvt_s_Gp(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitFcvt___Gp(Context, Emit, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitFcvt_u_Gp(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitFcvt___Gp(Context, Emit, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitFcvt___Gp(AILEmitterCtx Context, Action Emit, bool Signed)
|
2018-02-17 22:59:37 +01:00
|
|
|
{
|
|
|
|
AOpCodeSimdCvt Op = (AOpCodeSimdCvt)Context.CurrOp;
|
|
|
|
|
|
|
|
EmitVectorExtractF(Context, Op.Rn, 0, Op.Size);
|
|
|
|
|
2018-02-24 01:59:38 +01:00
|
|
|
Emit();
|
2018-02-17 22:59:37 +01:00
|
|
|
|
|
|
|
if (Signed)
|
|
|
|
{
|
|
|
|
EmitScalarFcvts(Context, Op.Size, 0);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
EmitScalarFcvtu(Context, Op.Size, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Context.CurrOp.RegisterSize == ARegisterSize.Int32)
|
|
|
|
{
|
|
|
|
Context.Emit(OpCodes.Conv_U8);
|
|
|
|
}
|
|
|
|
|
|
|
|
Context.EmitStintzr(Op.Rd);
|
|
|
|
}
|
|
|
|
|
2018-02-24 01:59:38 +01:00
|
|
|
private static void EmitFcvtzs_Gp_Fix(AILEmitterCtx Context)
|
2018-02-17 22:06:11 +01:00
|
|
|
{
|
2018-02-24 01:59:38 +01:00
|
|
|
EmitFcvtz__Gp_Fix(Context, true);
|
2018-02-17 22:06:11 +01:00
|
|
|
}
|
|
|
|
|
2018-02-24 01:59:38 +01:00
|
|
|
private static void EmitFcvtzu_Gp_Fix(AILEmitterCtx Context)
|
2018-02-17 22:06:11 +01:00
|
|
|
{
|
2018-02-24 01:59:38 +01:00
|
|
|
EmitFcvtz__Gp_Fix(Context, false);
|
2018-02-17 22:06:11 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitFcvtz__Gp_Fix(AILEmitterCtx Context, bool Signed)
|
|
|
|
{
|
|
|
|
AOpCodeSimdCvt Op = (AOpCodeSimdCvt)Context.CurrOp;
|
|
|
|
|
|
|
|
EmitVectorExtractF(Context, Op.Rn, 0, Op.Size);
|
|
|
|
|
|
|
|
if (Signed)
|
|
|
|
{
|
|
|
|
EmitScalarFcvts(Context, Op.Size, Op.FBits);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
EmitScalarFcvtu(Context, Op.Size, Op.FBits);
|
|
|
|
}
|
|
|
|
|
2018-02-18 05:57:33 +01:00
|
|
|
if (Context.CurrOp.RegisterSize == ARegisterSize.Int32)
|
|
|
|
{
|
|
|
|
Context.Emit(OpCodes.Conv_U8);
|
|
|
|
}
|
|
|
|
|
2018-02-17 22:06:11 +01:00
|
|
|
Context.EmitStintzr(Op.Rd);
|
|
|
|
}
|
|
|
|
|
2018-02-24 01:59:38 +01:00
|
|
|
private static void EmitVectorScvtf(AILEmitterCtx Context)
|
|
|
|
{
|
|
|
|
EmitVectorCvtf(Context, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitVectorUcvtf(AILEmitterCtx Context)
|
|
|
|
{
|
|
|
|
EmitVectorCvtf(Context, false);
|
|
|
|
}
|
|
|
|
|
2018-02-17 22:06:11 +01:00
|
|
|
private static void EmitVectorCvtf(AILEmitterCtx Context, bool Signed)
|
|
|
|
{
|
|
|
|
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
|
|
|
|
|
|
|
int SizeF = Op.Size & 1;
|
|
|
|
int SizeI = SizeF + 2;
|
|
|
|
|
|
|
|
int FBits = GetFBits(Context);
|
|
|
|
|
2018-07-14 18:13:02 +02:00
|
|
|
int Bytes = Op.GetBitsCount() >> 3;
|
2018-10-23 16:12:45 +02:00
|
|
|
int Elems = Bytes >> SizeI;
|
2018-02-17 22:06:11 +01:00
|
|
|
|
2018-10-23 16:12:45 +02:00
|
|
|
for (int Index = 0; Index < Elems; Index++)
|
2018-02-17 22:06:11 +01:00
|
|
|
{
|
|
|
|
EmitVectorExtract(Context, Op.Rn, Index, SizeI, Signed);
|
|
|
|
|
|
|
|
if (!Signed)
|
|
|
|
{
|
|
|
|
Context.Emit(OpCodes.Conv_R_Un);
|
|
|
|
}
|
|
|
|
|
|
|
|
Context.Emit(SizeF == 0
|
|
|
|
? OpCodes.Conv_R4
|
|
|
|
: OpCodes.Conv_R8);
|
|
|
|
|
|
|
|
EmitI2fFBitsMul(Context, SizeF, FBits);
|
|
|
|
|
|
|
|
EmitVectorInsertF(Context, Op.Rd, Index, SizeF);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Op.RegisterSize == ARegisterSize.SIMD64)
|
|
|
|
{
|
|
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-05-18 19:44:49 +02:00
|
|
|
private static void EmitScalarFcvtzs(AILEmitterCtx Context)
|
|
|
|
{
|
|
|
|
EmitScalarFcvtz(Context, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitScalarFcvtzu(AILEmitterCtx Context)
|
|
|
|
{
|
|
|
|
EmitScalarFcvtz(Context, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitScalarFcvtz(AILEmitterCtx Context, bool Signed)
|
|
|
|
{
|
|
|
|
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
|
|
|
|
|
|
|
int SizeF = Op.Size & 1;
|
|
|
|
int SizeI = SizeF + 2;
|
|
|
|
|
|
|
|
int FBits = GetFBits(Context);
|
|
|
|
|
|
|
|
EmitVectorExtractF(Context, Op.Rn, 0, SizeF);
|
|
|
|
|
|
|
|
EmitF2iFBitsMul(Context, SizeF, FBits);
|
|
|
|
|
|
|
|
if (SizeF == 0)
|
|
|
|
{
|
|
|
|
AVectorHelper.EmitCall(Context, Signed
|
|
|
|
? nameof(AVectorHelper.SatF32ToS32)
|
|
|
|
: nameof(AVectorHelper.SatF32ToU32));
|
|
|
|
}
|
|
|
|
else /* if (SizeF == 1) */
|
|
|
|
{
|
|
|
|
AVectorHelper.EmitCall(Context, Signed
|
|
|
|
? nameof(AVectorHelper.SatF64ToS64)
|
|
|
|
: nameof(AVectorHelper.SatF64ToU64));
|
|
|
|
}
|
|
|
|
|
|
|
|
if (SizeF == 0)
|
|
|
|
{
|
|
|
|
Context.Emit(OpCodes.Conv_U8);
|
|
|
|
}
|
|
|
|
|
|
|
|
EmitScalarSet(Context, Op.Rd, SizeI);
|
|
|
|
}
|
|
|
|
|
2018-02-24 01:59:38 +01:00
|
|
|
private static void EmitVectorFcvtzs(AILEmitterCtx Context)
|
|
|
|
{
|
|
|
|
EmitVectorFcvtz(Context, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitVectorFcvtzu(AILEmitterCtx Context)
|
|
|
|
{
|
|
|
|
EmitVectorFcvtz(Context, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitVectorFcvtz(AILEmitterCtx Context, bool Signed)
|
2018-02-17 22:06:11 +01:00
|
|
|
{
|
|
|
|
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
|
|
|
|
|
|
|
int SizeF = Op.Size & 1;
|
|
|
|
int SizeI = SizeF + 2;
|
|
|
|
|
|
|
|
int FBits = GetFBits(Context);
|
|
|
|
|
2018-07-14 18:13:02 +02:00
|
|
|
int Bytes = Op.GetBitsCount() >> 3;
|
2018-10-23 16:12:45 +02:00
|
|
|
int Elems = Bytes >> SizeI;
|
2018-02-17 22:06:11 +01:00
|
|
|
|
2018-10-23 16:12:45 +02:00
|
|
|
for (int Index = 0; Index < Elems; Index++)
|
2018-02-17 22:06:11 +01:00
|
|
|
{
|
|
|
|
EmitVectorExtractF(Context, Op.Rn, Index, SizeF);
|
|
|
|
|
|
|
|
EmitF2iFBitsMul(Context, SizeF, FBits);
|
|
|
|
|
|
|
|
if (SizeF == 0)
|
|
|
|
{
|
2018-05-12 01:10:27 +02:00
|
|
|
AVectorHelper.EmitCall(Context, Signed
|
|
|
|
? nameof(AVectorHelper.SatF32ToS32)
|
|
|
|
: nameof(AVectorHelper.SatF32ToU32));
|
2018-02-17 22:06:11 +01:00
|
|
|
}
|
|
|
|
else /* if (SizeF == 1) */
|
|
|
|
{
|
2018-05-12 01:10:27 +02:00
|
|
|
AVectorHelper.EmitCall(Context, Signed
|
|
|
|
? nameof(AVectorHelper.SatF64ToS64)
|
|
|
|
: nameof(AVectorHelper.SatF64ToU64));
|
2018-02-17 22:06:11 +01:00
|
|
|
}
|
|
|
|
|
2018-02-18 05:57:33 +01:00
|
|
|
if (SizeF == 0)
|
|
|
|
{
|
|
|
|
Context.Emit(OpCodes.Conv_U8);
|
|
|
|
}
|
|
|
|
|
2018-02-17 22:06:11 +01:00
|
|
|
EmitVectorInsert(Context, Op.Rd, Index, SizeI);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Op.RegisterSize == ARegisterSize.SIMD64)
|
|
|
|
{
|
|
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitScalarFcvts(AILEmitterCtx Context, int Size, int FBits)
|
|
|
|
{
|
|
|
|
if (Size < 0 || Size > 1)
|
|
|
|
{
|
|
|
|
throw new ArgumentOutOfRangeException(nameof(Size));
|
|
|
|
}
|
|
|
|
|
|
|
|
EmitF2iFBitsMul(Context, Size, FBits);
|
|
|
|
|
|
|
|
if (Context.CurrOp.RegisterSize == ARegisterSize.Int32)
|
|
|
|
{
|
|
|
|
if (Size == 0)
|
|
|
|
{
|
2018-05-12 01:10:27 +02:00
|
|
|
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.SatF32ToS32));
|
2018-02-17 22:06:11 +01:00
|
|
|
}
|
|
|
|
else /* if (Size == 1) */
|
|
|
|
{
|
2018-05-12 01:10:27 +02:00
|
|
|
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.SatF64ToS32));
|
2018-02-17 22:06:11 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (Size == 0)
|
|
|
|
{
|
2018-05-12 01:10:27 +02:00
|
|
|
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.SatF32ToS64));
|
2018-02-17 22:06:11 +01:00
|
|
|
}
|
|
|
|
else /* if (Size == 1) */
|
|
|
|
{
|
2018-05-12 01:10:27 +02:00
|
|
|
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.SatF64ToS64));
|
2018-02-17 22:06:11 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitScalarFcvtu(AILEmitterCtx Context, int Size, int FBits)
|
|
|
|
{
|
|
|
|
if (Size < 0 || Size > 1)
|
|
|
|
{
|
|
|
|
throw new ArgumentOutOfRangeException(nameof(Size));
|
|
|
|
}
|
|
|
|
|
|
|
|
EmitF2iFBitsMul(Context, Size, FBits);
|
|
|
|
|
|
|
|
if (Context.CurrOp.RegisterSize == ARegisterSize.Int32)
|
|
|
|
{
|
|
|
|
if (Size == 0)
|
|
|
|
{
|
2018-05-12 01:10:27 +02:00
|
|
|
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.SatF32ToU32));
|
2018-02-17 22:06:11 +01:00
|
|
|
}
|
|
|
|
else /* if (Size == 1) */
|
|
|
|
{
|
2018-05-12 01:10:27 +02:00
|
|
|
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.SatF64ToU32));
|
2018-02-17 22:06:11 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (Size == 0)
|
|
|
|
{
|
2018-05-12 01:10:27 +02:00
|
|
|
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.SatF32ToU64));
|
2018-02-17 22:06:11 +01:00
|
|
|
}
|
|
|
|
else /* if (Size == 1) */
|
|
|
|
{
|
2018-05-12 01:10:27 +02:00
|
|
|
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.SatF64ToU64));
|
2018-02-17 22:06:11 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitF2iFBitsMul(AILEmitterCtx Context, int Size, int FBits)
|
|
|
|
{
|
|
|
|
if (FBits != 0)
|
|
|
|
{
|
|
|
|
if (Size == 0)
|
|
|
|
{
|
2018-10-23 16:12:45 +02:00
|
|
|
Context.EmitLdc_R4(MathF.Pow(2f, FBits));
|
2018-02-17 22:06:11 +01:00
|
|
|
}
|
|
|
|
else if (Size == 1)
|
|
|
|
{
|
2018-10-23 16:12:45 +02:00
|
|
|
Context.EmitLdc_R8(Math.Pow(2d, FBits));
|
2018-02-17 22:06:11 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
throw new ArgumentOutOfRangeException(nameof(Size));
|
|
|
|
}
|
|
|
|
|
|
|
|
Context.Emit(OpCodes.Mul);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitI2fFBitsMul(AILEmitterCtx Context, int Size, int FBits)
|
|
|
|
{
|
|
|
|
if (FBits != 0)
|
|
|
|
{
|
|
|
|
if (Size == 0)
|
|
|
|
{
|
2018-10-23 16:12:45 +02:00
|
|
|
Context.EmitLdc_R4(1f / MathF.Pow(2f, FBits));
|
2018-02-17 22:06:11 +01:00
|
|
|
}
|
|
|
|
else if (Size == 1)
|
|
|
|
{
|
2018-10-23 16:12:45 +02:00
|
|
|
Context.EmitLdc_R8(1d / Math.Pow(2d, FBits));
|
2018-02-17 22:06:11 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
throw new ArgumentOutOfRangeException(nameof(Size));
|
|
|
|
}
|
|
|
|
|
|
|
|
Context.Emit(OpCodes.Mul);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, Umlsl_V, Saddl_V, Ssubl_V, Usubl_V instructions; add 8 FP & 16 S/Umlal_V, S/Umlsl_V, S/Uaddl_V, S/Usubl_V Tests. (#390)
* Update AOpCodeTable.cs
* Update AInstEmitSimdCvt.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update Instructions.cs
* Update CpuTestSimdReg.cs
* Update CpuTestSimd.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update Instructions.cs
* Update CpuTestSimdReg.cs
* Add QCFlagBit.
* Add QCFlagBit.
2018-09-01 16:52:51 +02:00
|
|
|
}
|