2020-03-11 01:49:27 +01:00
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namespace ARMeilleure.Decoders
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{
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class OpCode32SimdRegLong : OpCode32SimdReg
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{
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public bool Polynomial { get; private set; }
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public OpCode32SimdRegLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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Q = false;
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RegisterSize = RegisterSize.Simd64;
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Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths). (#1577)
* Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths).
No test provided (i.e. draft).
* Ptc InternalVersion = 1577
2020-10-13 22:41:33 +02:00
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2020-03-11 01:49:27 +01:00
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Polynomial = ((opCode >> 9) & 0x1) != 0;
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Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths). (#1577)
* Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths).
No test provided (i.e. draft).
* Ptc InternalVersion = 1577
2020-10-13 22:41:33 +02:00
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// Subclasses have their own handling of Vx to account for before checking.
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if (GetType() == typeof(OpCode32SimdRegLong) && DecoderHelper.VectorArgumentsInvalid(true, Vd))
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{
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Instruction = InstDescriptor.Undefined;
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}
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2020-03-11 01:49:27 +01:00
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}
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}
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}
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