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Add Fpscr.Qc = 1 if sat. for Vqrshrn & Vqrshrun.

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This commit is contained in:
LDj3SNuD 2020-07-27 16:56:59 +02:00
parent a4c36873f7
commit 5f418d0752
4 changed files with 19 additions and 9 deletions
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2
ARMeilleure/Instructions/InstEmitSimdShift32.cs
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@ -289,7 +289,7 @@ namespace ARMeilleure.Instructions
context.BranchIfFalse(lblNoSat, context.BitwiseOr(gt, lt));
// TODO: Set QC (to 1) on FPSCR here.
context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
context.MarkLabel(lblNoSat);

5
ARMeilleure/Instructions/NativeInterface.cs
View file

@ -145,6 +145,11 @@ namespace ARMeilleure.Instructions
GetContext().Fpsr = (FPSR)value;
}
public static void SetFpsrQc()
{
GetContext().Fpsr |= FPSR.Qc;
}
public static void SetFpscr(uint fpscr)
{
var context = GetContext();

1
ARMeilleure/Translation/Delegates.cs
View file

@ -131,6 +131,7 @@ namespace ARMeilleure.Translation
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpcr)));
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpscr))); // A32 only.
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsr)));
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc))); // A32 only.
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetTpidrEl0)));
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetTpidrEl032))); // A32 only.
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SupervisorCall)));

20
Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs
View file

@ -173,7 +173,7 @@ namespace Ryujinx.Tests.Cpu
public void Vshl_Imm([Values(0u)] uint rd,
[Values(2u, 0u)] uint rm,
[Values(0u, 1u, 2u, 3u)] uint size,
[Random(RndCnt), Values(0u)] uint shiftImm,
[Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
[Random(RndCnt)] ulong z,
[Random(RndCnt)] ulong a,
[Random(RndCnt)] ulong b,
@ -207,7 +207,7 @@ namespace Ryujinx.Tests.Cpu
public void Vshrn_Imm([Values(0u, 1u)] uint rd,
[Values(2u, 0u)] uint rm,
[Values(0u, 1u, 2u)] uint size,
[Random(RndCnt), Values(0u)] uint shiftImm,
[Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
[Random(RndCnt)] ulong z,
[Random(RndCnt)] ulong a,
[Random(RndCnt)] ulong b)
@ -234,7 +234,7 @@ namespace Ryujinx.Tests.Cpu
public void Vqrshrn_Imm([Values(0u, 1u)] uint rd,
[Values(2u, 0u)] uint rm,
[Values(0u, 1u, 2u)] uint size,
[Random(RndCnt), Values(0u)] uint shiftImm,
[Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
[Random(RndCnt)] ulong z,
[Random(RndCnt)] ulong a,
[Random(RndCnt)] ulong b,
@ -258,16 +258,18 @@ namespace Ryujinx.Tests.Cpu
V128 v1 = MakeVectorE0E1(a, z);
V128 v2 = MakeVectorE0E1(b, z);
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
int fpscr = (int)TestContext.CurrentContext.Random.NextUInt() & (int)Fpsr.Qc;
CompareAgainstUnicorn();
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, fpscr: fpscr);
CompareAgainstUnicorn(fpsrMask: Fpsr.Qc);
}
[Test, Pairwise, Description("VQRSHRUN.<type><size> <Vd>, <Vm>, #<imm>")]
public void Vqrshrun_Imm([Values(0u, 1u)] uint rd,
[Values(2u, 0u)] uint rm,
[Values(0u, 1u, 2u)] uint size,
[Random(RndCnt), Values(0u)] uint shiftImm,
[Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
[Random(RndCnt)] ulong z,
[Random(RndCnt)] ulong a,
[Random(RndCnt)] ulong b)
@ -285,9 +287,11 @@ namespace Ryujinx.Tests.Cpu
V128 v1 = MakeVectorE0E1(a, z);
V128 v2 = MakeVectorE0E1(b, z);
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
int fpscr = (int)TestContext.CurrentContext.Random.NextUInt() & (int)Fpsr.Qc;
CompareAgainstUnicorn();
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, fpscr: fpscr);
CompareAgainstUnicorn(fpsrMask: Fpsr.Qc);
}
#endif
}