De-tile GOB when DMA copying from block linear to pitch kind memory regions (#3207)
* De-tile GOB when DMA copying from block linear to pitch kind memory regions * XML docs + nits * Remove using * No flush for regular buffer copies * Add back ulong casts, fix regression due to oversight
This commit is contained in:
gdkchan
GitHub
parent
d461d4f68b
commit
79408b68c3
8 changed files with 430 additions and 33 deletions
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@ -1,7 +1,7 @@
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using Ryujinx.Common;
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using Ryujinx.Common.Logging;
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using Ryujinx.Graphics.Device;
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using Ryujinx.Graphics.Gpu.Engine.Threed;
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using Ryujinx.Graphics.Gpu.Memory;
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using Ryujinx.Graphics.Texture;
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using System;
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using System.Collections.Generic;
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@ -330,11 +330,95 @@ namespace Ryujinx.Graphics.Gpu.Engine.Dma
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{
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// TODO: Implement remap functionality.
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// Buffer to buffer copy.
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memoryManager.Physical.BufferCache.CopyBuffer(memoryManager, srcGpuVa, dstGpuVa, size);
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bool srcIsPitchKind = memoryManager.GetKind(srcGpuVa).IsPitch();
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bool dstIsPitchKind = memoryManager.GetKind(dstGpuVa).IsPitch();
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if (!srcIsPitchKind && dstIsPitchKind)
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{
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CopyGobBlockLinearToLinear(memoryManager, srcGpuVa, dstGpuVa, size);
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}
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else if (srcIsPitchKind && !dstIsPitchKind)
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{
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CopyGobLinearToBlockLinear(memoryManager, srcGpuVa, dstGpuVa, size);
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}
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else
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{
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memoryManager.Physical.BufferCache.CopyBuffer(memoryManager, srcGpuVa, dstGpuVa, size);
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}
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}
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}
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}
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/// <summary>
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/// Copies block linear data with block linear GOBs to a block linear destination with linear GOBs.
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/// </summary>
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/// <param name="memoryManager">GPU memory manager</param>
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/// <param name="srcGpuVa">Source GPU virtual address</param>
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/// <param name="dstGpuVa">Destination GPU virtual address</param>
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/// <param name="size">Size in bytes of the copy</param>
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private static void CopyGobBlockLinearToLinear(MemoryManager memoryManager, ulong srcGpuVa, ulong dstGpuVa, ulong size)
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{
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if (((srcGpuVa | dstGpuVa | size) & 0xf) == 0)
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{
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for (ulong offset = 0; offset < size; offset += 16)
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{
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Vector128<byte> data = memoryManager.Read<Vector128<byte>>(ConvertGobLinearToBlockLinearAddress(srcGpuVa + offset), true);
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memoryManager.Write(dstGpuVa + offset, data);
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}
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}
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else
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{
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for (ulong offset = 0; offset < size; offset++)
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{
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byte data = memoryManager.Read<byte>(ConvertGobLinearToBlockLinearAddress(srcGpuVa + offset), true);
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memoryManager.Write(dstGpuVa + offset, data);
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}
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}
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}
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/// <summary>
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/// Copies block linear data with linear GOBs to a block linear destination with block linear GOBs.
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/// </summary>
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/// <param name="memoryManager">GPU memory manager</param>
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/// <param name="srcGpuVa">Source GPU virtual address</param>
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/// <param name="dstGpuVa">Destination GPU virtual address</param>
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/// <param name="size">Size in bytes of the copy</param>
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private static void CopyGobLinearToBlockLinear(MemoryManager memoryManager, ulong srcGpuVa, ulong dstGpuVa, ulong size)
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{
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if (((srcGpuVa | dstGpuVa | size) & 0xf) == 0)
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{
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for (ulong offset = 0; offset < size; offset += 16)
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{
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Vector128<byte> data = memoryManager.Read<Vector128<byte>>(srcGpuVa + offset, true);
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memoryManager.Write(ConvertGobLinearToBlockLinearAddress(dstGpuVa + offset), data);
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}
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}
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else
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{
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for (ulong offset = 0; offset < size; offset++)
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{
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byte data = memoryManager.Read<byte>(srcGpuVa + offset, true);
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memoryManager.Write(ConvertGobLinearToBlockLinearAddress(dstGpuVa + offset), data);
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}
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}
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}
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/// <summary>
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/// Calculates the GOB block linear address from a linear address.
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/// </summary>
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/// <param name="address">Linear address</param>
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/// <returns>Block linear address</returns>
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private static ulong ConvertGobLinearToBlockLinearAddress(ulong address)
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{
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// y2 y1 y0 x5 x4 x3 x2 x1 x0 -> x5 y2 y1 x4 y0 x3 x2 x1 x0
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return (address & ~0x1f0UL) |
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((address & 0x40) >> 2) |
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((address & 0x10) << 1) |
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((address & 0x180) >> 1) |
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((address & 0x20) << 3);
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}
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/// <summary>
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/// Performs a buffer to buffer, or buffer to texture copy, then optionally releases a semaphore.
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/// </summary>
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@ -7,7 +7,6 @@ using Ryujinx.Graphics.Gpu.Engine.Types;
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using Ryujinx.Graphics.Gpu.Image;
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using Ryujinx.Graphics.Gpu.Memory;
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using Ryujinx.Graphics.Texture;
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using Ryujinx.Memory;
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using Ryujinx.Memory.Range;
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using System;
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using System.Collections.Generic;
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@ -264,7 +264,8 @@ namespace Ryujinx.Graphics.Gpu.Memory
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/// <param name="pa">CPU virtual address to map into</param>
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/// <param name="va">GPU virtual address to be mapped</param>
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/// <param name="size">Size in bytes of the mapping</param>
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public void Map(ulong pa, ulong va, ulong size)
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/// <param name="kind">Kind of the resource located at the mapping</param>
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public void Map(ulong pa, ulong va, ulong size, PteKind kind)
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{
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lock (_pageTable)
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{
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@ -272,7 +273,7 @@ namespace Ryujinx.Graphics.Gpu.Memory
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for (ulong offset = 0; offset < size; offset += PageSize)
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{
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SetPte(va + offset, pa + offset);
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SetPte(va + offset, PackPte(pa + offset, kind));
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}
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}
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}
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@ -462,14 +463,37 @@ namespace Ryujinx.Graphics.Gpu.Memory
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return PteUnmapped;
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}
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ulong baseAddress = GetPte(va);
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ulong pte = GetPte(va);
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if (baseAddress == PteUnmapped)
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if (pte == PteUnmapped)
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{
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return PteUnmapped;
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}
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return baseAddress + (va & PageMask);
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return UnpackPaFromPte(pte) + (va & PageMask);
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}
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/// <summary>
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/// Gets the kind of a given memory page.
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/// This might indicate the type of resource that can be allocated on the page, and also texture tiling.
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/// </summary>
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/// <param name="va">GPU virtual address</param>
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/// <returns>Kind of the memory page</returns>
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public PteKind GetKind(ulong va)
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{
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if (!ValidateAddress(va))
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{
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return PteKind.Invalid;
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}
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ulong pte = GetPte(va);
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if (pte == PteUnmapped)
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{
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return PteKind.Invalid;
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}
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return UnpackKindFromPte(pte);
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}
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/// <summary>
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@ -512,5 +536,36 @@ namespace Ryujinx.Graphics.Gpu.Memory
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_pageTable[l0][l1] = pte;
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}
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/// <summary>
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/// Creates a page table entry from a physical address and kind.
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/// </summary>
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/// <param name="pa">Physical address</param>
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/// <param name="kind">Kind</param>
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/// <returns>Page table entry</returns>
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private static ulong PackPte(ulong pa, PteKind kind)
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{
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return pa | ((ulong)kind << 56);
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}
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/// <summary>
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/// Unpacks kind from a page table entry.
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/// </summary>
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/// <param name="pte">Page table entry</param>
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/// <returns>Kind</returns>
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private static PteKind UnpackKindFromPte(ulong pte)
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{
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return (PteKind)(pte >> 56);
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}
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/// <summary>
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/// Unpacks physical address from a page table entry.
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/// </summary>
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/// <param name="pte">Page table entry</param>
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/// <returns>Physical address</returns>
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private static ulong UnpackPaFromPte(ulong pte)
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{
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return pte & 0xffffffffffffffUL;
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}
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}
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}
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268
Ryujinx.Graphics.Gpu/Memory/PteKind.cs
Normal file
268
Ryujinx.Graphics.Gpu/Memory/PteKind.cs
Normal file
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@ -0,0 +1,268 @@
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namespace Ryujinx.Graphics.Gpu.Memory
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{
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/// <summary>
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/// Kind of the resource at the given memory mapping.
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/// </summary>
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public enum PteKind : byte
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{
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Invalid = 0xff,
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Pitch = 0x00,
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Z16 = 0x01,
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Z162C = 0x02,
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Z16MS22C = 0x03,
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Z16MS42C = 0x04,
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Z16MS82C = 0x05,
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Z16MS162C = 0x06,
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Z162Z = 0x07,
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Z16MS22Z = 0x08,
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Z16MS42Z = 0x09,
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Z16MS82Z = 0x0a,
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Z16MS162Z = 0x0b,
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Z162CZ = 0x36,
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Z16MS22CZ = 0x37,
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Z16MS42CZ = 0x38,
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Z16MS82CZ = 0x39,
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Z16MS162CZ = 0x5f,
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Z164CZ = 0x0c,
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Z16MS24CZ = 0x0d,
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Z16MS44CZ = 0x0e,
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Z16MS84CZ = 0x0f,
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Z16MS164CZ = 0x10,
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S8Z24 = 0x11,
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S8Z241Z = 0x12,
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S8Z24MS21Z = 0x13,
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S8Z24MS41Z = 0x14,
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S8Z24MS81Z = 0x15,
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S8Z24MS161Z = 0x16,
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S8Z242CZ = 0x17,
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S8Z24MS22CZ = 0x18,
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S8Z24MS42CZ = 0x19,
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S8Z24MS82CZ = 0x1a,
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S8Z24MS162CZ = 0x1b,
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S8Z242CS = 0x1c,
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S8Z24MS22CS = 0x1d,
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S8Z24MS42CS = 0x1e,
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S8Z24MS82CS = 0x1f,
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S8Z24MS162CS = 0x20,
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S8Z244CSZV = 0x21,
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S8Z24MS24CSZV = 0x22,
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S8Z24MS44CSZV = 0x23,
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S8Z24MS84CSZV = 0x24,
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S8Z24MS164CSZV = 0x25,
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V8Z24MS4VC12 = 0x26,
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V8Z24MS4VC4 = 0x27,
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V8Z24MS8VC8 = 0x28,
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V8Z24MS8VC24 = 0x29,
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V8Z24MS4VC121ZV = 0x2e,
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V8Z24MS4VC41ZV = 0x2f,
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V8Z24MS8VC81ZV = 0x30,
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V8Z24MS8VC241ZV = 0x31,
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V8Z24MS4VC122CS = 0x32,
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V8Z24MS4VC42CS = 0x33,
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V8Z24MS8VC82CS = 0x34,
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V8Z24MS8VC242CS = 0x35,
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V8Z24MS4VC122CZV = 0x3a,
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V8Z24MS4VC42CZV = 0x3b,
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V8Z24MS8VC82CZV = 0x3c,
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V8Z24MS8VC242CZV = 0x3d,
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V8Z24MS4VC122ZV = 0x3e,
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V8Z24MS4VC42ZV = 0x3f,
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V8Z24MS8VC82ZV = 0x40,
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V8Z24MS8VC242ZV = 0x41,
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V8Z24MS4VC124CSZV = 0x42,
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V8Z24MS4VC44CSZV = 0x43,
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V8Z24MS8VC84CSZV = 0x44,
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V8Z24MS8VC244CSZV = 0x45,
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Z24S8 = 0x46,
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Z24S81Z = 0x47,
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Z24S8MS21Z = 0x48,
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Z24S8MS41Z = 0x49,
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Z24S8MS81Z = 0x4a,
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Z24S8MS161Z = 0x4b,
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Z24S82CS = 0x4c,
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Z24S8MS22CS = 0x4d,
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Z24S8MS42CS = 0x4e,
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Z24S8MS82CS = 0x4f,
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Z24S8MS162CS = 0x50,
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Z24S82CZ = 0x51,
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Z24S8MS22CZ = 0x52,
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Z24S8MS42CZ = 0x53,
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Z24S8MS82CZ = 0x54,
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Z24S8MS162CZ = 0x55,
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Z24S84CSZV = 0x56,
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Z24S8MS24CSZV = 0x57,
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Z24S8MS44CSZV = 0x58,
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Z24S8MS84CSZV = 0x59,
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Z24S8MS164CSZV = 0x5a,
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Z24V8MS4VC12 = 0x5b,
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Z24V8MS4VC4 = 0x5c,
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Z24V8MS8VC8 = 0x5d,
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Z24V8MS8VC24 = 0x5e,
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YUVB8C12Y = 0x60,
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YUVB8C22Y = 0x61,
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YUVB10C12Y = 0x62,
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YUVB10C22Y = 0x6b,
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YUVB12C12Y = 0x6c,
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YUVB12C22Y = 0x6d,
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Z24V8MS4VC121ZV = 0x63,
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Z24V8MS4VC41ZV = 0x64,
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Z24V8MS8VC81ZV = 0x65,
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Z24V8MS8VC241ZV = 0x66,
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Z24V8MS4VC122CS = 0x67,
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Z24V8MS4VC42CS = 0x68,
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Z24V8MS8VC82CS = 0x69,
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Z24V8MS8VC242CS = 0x6a,
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Z24V8MS4VC122CZV = 0x6f,
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Z24V8MS4VC42CZV = 0x70,
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Z24V8MS8VC82CZV = 0x71,
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Z24V8MS8VC242CZV = 0x72,
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Z24V8MS4VC122ZV = 0x73,
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Z24V8MS4VC42ZV = 0x74,
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Z24V8MS8VC82ZV = 0x75,
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Z24V8MS8VC242ZV = 0x76,
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Z24V8MS4VC124CSZV = 0x77,
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Z24V8MS4VC44CSZV = 0x78,
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Z24V8MS8VC84CSZV = 0x79,
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Z24V8MS8VC244CSZV = 0x7a,
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ZF32 = 0x7b,
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ZF321Z = 0x7c,
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ZF32MS21Z = 0x7d,
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ZF32MS41Z = 0x7e,
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ZF32MS81Z = 0x7f,
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ZF32MS161Z = 0x80,
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ZF322CS = 0x81,
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ZF32MS22CS = 0x82,
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ZF32MS42CS = 0x83,
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ZF32MS82CS = 0x84,
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ZF32MS162CS = 0x85,
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ZF322CZ = 0x86,
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ZF32MS22CZ = 0x87,
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ZF32MS42CZ = 0x88,
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ZF32MS82CZ = 0x89,
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ZF32MS162CZ = 0x8a,
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X8Z24X16V8S8MS4VC12 = 0x8b,
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X8Z24X16V8S8MS4VC4 = 0x8c,
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X8Z24X16V8S8MS8VC8 = 0x8d,
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X8Z24X16V8S8MS8VC24 = 0x8e,
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X8Z24X16V8S8MS4VC121CS = 0x8f,
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X8Z24X16V8S8MS4VC41CS = 0x90,
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X8Z24X16V8S8MS8VC81CS = 0x91,
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X8Z24X16V8S8MS8VC241CS = 0x92,
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X8Z24X16V8S8MS4VC121ZV = 0x97,
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X8Z24X16V8S8MS4VC41ZV = 0x98,
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X8Z24X16V8S8MS8VC81ZV = 0x99,
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X8Z24X16V8S8MS8VC241ZV = 0x9a,
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X8Z24X16V8S8MS4VC121CZV = 0x9b,
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X8Z24X16V8S8MS4VC41CZV = 0x9c,
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X8Z24X16V8S8MS8VC81CZV = 0x9d,
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X8Z24X16V8S8MS8VC241CZV = 0x9e,
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X8Z24X16V8S8MS4VC122CS = 0x9f,
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X8Z24X16V8S8MS4VC42CS = 0xa0,
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X8Z24X16V8S8MS8VC82CS = 0xa1,
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X8Z24X16V8S8MS8VC242CS = 0xa2,
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X8Z24X16V8S8MS4VC122CSZV = 0xa3,
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X8Z24X16V8S8MS4VC42CSZV = 0xa4,
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X8Z24X16V8S8MS8VC82CSZV = 0xa5,
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X8Z24X16V8S8MS8VC242CSZV = 0xa6,
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ZF32X16V8S8MS4VC12 = 0xa7,
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ZF32X16V8S8MS4VC4 = 0xa8,
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ZF32X16V8S8MS8VC8 = 0xa9,
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ZF32X16V8S8MS8VC24 = 0xaa,
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ZF32X16V8S8MS4VC121CS = 0xab,
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ZF32X16V8S8MS4VC41CS = 0xac,
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ZF32X16V8S8MS8VC81CS = 0xad,
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ZF32X16V8S8MS8VC241CS = 0xae,
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ZF32X16V8S8MS4VC121ZV = 0xb3,
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ZF32X16V8S8MS4VC41ZV = 0xb4,
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ZF32X16V8S8MS8VC81ZV = 0xb5,
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ZF32X16V8S8MS8VC241ZV = 0xb6,
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ZF32X16V8S8MS4VC121CZV = 0xb7,
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ZF32X16V8S8MS4VC41CZV = 0xb8,
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ZF32X16V8S8MS8VC81CZV = 0xb9,
|
||||
ZF32X16V8S8MS8VC241CZV = 0xba,
|
||||
ZF32X16V8S8MS4VC122CS = 0xbb,
|
||||
ZF32X16V8S8MS4VC42CS = 0xbc,
|
||||
ZF32X16V8S8MS8VC82CS = 0xbd,
|
||||
ZF32X16V8S8MS8VC242CS = 0xbe,
|
||||
ZF32X16V8S8MS4VC122CSZV = 0xbf,
|
||||
ZF32X16V8S8MS4VC42CSZV = 0xc0,
|
||||
ZF32X16V8S8MS8VC82CSZV = 0xc1,
|
||||
ZF32X16V8S8MS8VC242CSZV = 0xc2,
|
||||
ZF32X24S8 = 0xc3,
|
||||
ZF32X24S81CS = 0xc4,
|
||||
ZF32X24S8MS21CS = 0xc5,
|
||||
ZF32X24S8MS41CS = 0xc6,
|
||||
ZF32X24S8MS81CS = 0xc7,
|
||||
ZF32X24S8MS161CS = 0xc8,
|
||||
ZF32X24S82CSZV = 0xce,
|
||||
ZF32X24S8MS22CSZV = 0xcf,
|
||||
ZF32X24S8MS42CSZV = 0xd0,
|
||||
ZF32X24S8MS82CSZV = 0xd1,
|
||||
ZF32X24S8MS162CSZV = 0xd2,
|
||||
ZF32X24S82CS = 0xd3,
|
||||
ZF32X24S8MS22CS = 0xd4,
|
||||
ZF32X24S8MS42CS = 0xd5,
|
||||
ZF32X24S8MS82CS = 0xd6,
|
||||
ZF32X24S8MS162CS = 0xd7,
|
||||
S8 = 0x2a,
|
||||
S82S = 0x2b,
|
||||
Generic16Bx2 = 0xfe,
|
||||
C322C = 0xd8,
|
||||
C322CBR = 0xd9,
|
||||
C322CBA = 0xda,
|
||||
C322CRA = 0xdb,
|
||||
C322BRA = 0xdc,
|
||||
C32MS22C = 0xdd,
|
||||
C32MS22CBR = 0xde,
|
||||
C32MS24CBRA = 0xcc,
|
||||
C32MS42C = 0xdf,
|
||||
C32MS42CBR = 0xe0,
|
||||
C32MS42CBA = 0xe1,
|
||||
C32MS42CRA = 0xe2,
|
||||
C32MS42BRA = 0xe3,
|
||||
C32MS44CBRA = 0x2c,
|
||||
C32MS8MS162C = 0xe4,
|
||||
C32MS8MS162CRA = 0xe5,
|
||||
C642C = 0xe6,
|
||||
C642CBR = 0xe7,
|
||||
C642CBA = 0xe8,
|
||||
C642CRA = 0xe9,
|
||||
C642BRA = 0xea,
|
||||
C64MS22C = 0xeb,
|
||||
C64MS22CBR = 0xec,
|
||||
C64MS24CBRA = 0xcd,
|
||||
C64MS42C = 0xed,
|
||||
C64MS42CBR = 0xee,
|
||||
C64MS42CBA = 0xef,
|
||||
C64MS42CRA = 0xf0,
|
||||
C64MS42BRA = 0xf1,
|
||||
C64MS44CBRA = 0x2d,
|
||||
C64MS8MS162C = 0xf2,
|
||||
C64MS8MS162CRA = 0xf3,
|
||||
C1282C = 0xf4,
|
||||
C1282CR = 0xf5,
|
||||
C128MS22C = 0xf6,
|
||||
C128MS22CR = 0xf7,
|
||||
C128MS42C = 0xf8,
|
||||
C128MS42CR = 0xf9,
|
||||
C128MS8MS162C = 0xfa,
|
||||
C128MS8MS162CR = 0xfb,
|
||||
X8C24 = 0xfc,
|
||||
PitchNoSwizzle = 0xfd,
|
||||
SmSkedMessage = 0xca,
|
||||
SmHostMessage = 0xcb
|
||||
}
|
||||
|
||||
static class PteKindExtensions
|
||||
{
|
||||
/// <summary>
|
||||
/// Checks if the kind is pitch.
|
||||
/// </summary>
|
||||
/// <param name="kind">Kind to check</param>
|
||||
/// <returns>True if pitch, false otherwise</returns>
|
||||
public static bool IsPitch(this PteKind kind)
|
||||
{
|
||||
return kind == PteKind.Pitch || kind == PteKind.PitchNoSwizzle;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
namespace Ryujinx.Graphics.Gpu.Memory
|
||||
{
|
||||
/// <summary>
|
||||
/// Name of a GPU resource.
|
||||
/// </summary>
|
||||
public enum ResourceName
|
||||
{
|
||||
Buffer,
|
||||
Texture,
|
||||
TexturePool,
|
||||
SamplerPool
|
||||
}
|
||||
}
|
||||
|
|
@ -232,7 +232,7 @@ namespace Ryujinx.HLE.HOS.Services.Nv.NvDrvServices.NvHostAsGpu
|
|||
ulong virtualAddress = arguments.Offset + arguments.BufferOffset;
|
||||
|
||||
physicalAddress += arguments.BufferOffset;
|
||||
_asContext.Gmm.Map(physicalAddress, virtualAddress, arguments.MappingSize);
|
||||
_asContext.Gmm.Map(physicalAddress, virtualAddress, arguments.MappingSize, (PteKind)arguments.Kind);
|
||||
|
||||
return NvInternalResult.Success;
|
||||
}
|
||||
|
|
@ -282,7 +282,7 @@ namespace Ryujinx.HLE.HOS.Services.Nv.NvDrvServices.NvHostAsGpu
|
|||
{
|
||||
if (_asContext.ValidateFixedBuffer(arguments.Offset, size, pageSize))
|
||||
{
|
||||
_asContext.Gmm.Map(physicalAddress, arguments.Offset, size);
|
||||
_asContext.Gmm.Map(physicalAddress, arguments.Offset, size, (PteKind)arguments.Kind);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -301,7 +301,7 @@ namespace Ryujinx.HLE.HOS.Services.Nv.NvDrvServices.NvHostAsGpu
|
|||
_memoryAllocator.AllocateRange(va, size, freeAddressStartPosition);
|
||||
}
|
||||
|
||||
_asContext.Gmm.Map(physicalAddress, va, size);
|
||||
_asContext.Gmm.Map(physicalAddress, va, size, (PteKind)arguments.Kind);
|
||||
arguments.Offset = va;
|
||||
}
|
||||
|
||||
|
|
@ -366,26 +366,30 @@ namespace Ryujinx.HLE.HOS.Services.Nv.NvDrvServices.NvHostAsGpu
|
|||
|
||||
for (int index = 0; index < arguments.Length; index++)
|
||||
{
|
||||
ulong mapOffs = (ulong)arguments[index].MapOffset << 16;
|
||||
ulong gpuVa = (ulong)arguments[index].GpuOffset << 16;
|
||||
ulong size = (ulong)arguments[index].Pages << 16;
|
||||
ref RemapArguments argument = ref arguments[index];
|
||||
ulong gpuVa = (ulong)argument.GpuOffset << 16;
|
||||
ulong size = (ulong)argument.Pages << 16;
|
||||
int nvmapHandle = argument.NvMapHandle;
|
||||
|
||||
if (arguments[index].NvMapHandle == 0)
|
||||
if (nvmapHandle == 0)
|
||||
{
|
||||
gmm.Unmap(gpuVa, size);
|
||||
}
|
||||
else
|
||||
{
|
||||
NvMapHandle map = NvMapDeviceFile.GetMapFromHandle(Owner, arguments[index].NvMapHandle);
|
||||
ulong mapOffs = (ulong)argument.MapOffset << 16;
|
||||
PteKind kind = (PteKind)argument.Kind;
|
||||
|
||||
NvMapHandle map = NvMapDeviceFile.GetMapFromHandle(Owner, nvmapHandle);
|
||||
|
||||
if (map == null)
|
||||
{
|
||||
Logger.Warning?.Print(LogClass.ServiceNv, $"Invalid NvMap handle 0x{arguments[index].NvMapHandle:x8}!");
|
||||
Logger.Warning?.Print(LogClass.ServiceNv, $"Invalid NvMap handle 0x{nvmapHandle:x8}!");
|
||||
|
||||
return NvInternalResult.InvalidInput;
|
||||
}
|
||||
|
||||
gmm.Map(mapOffs + map.Address, gpuVa, size);
|
||||
gmm.Map(mapOffs + map.Address, gpuVa, size, kind);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -251,7 +251,7 @@ namespace Ryujinx.HLE.HOS.Services.Nv.NvDrvServices.NvHostChannel
|
|||
if (va != NvMemoryAllocator.PteUnmapped && va <= uint.MaxValue && (va + (uint)map.Size) <= uint.MaxValue)
|
||||
{
|
||||
_host1xContext.MemoryAllocator.AllocateRange(va, (uint)map.Size, freeAddressStartPosition);
|
||||
_host1xContext.Smmu.Map(map.Address, va, (uint)map.Size);
|
||||
_host1xContext.Smmu.Map(map.Address, va, (uint)map.Size, PteKind.Pitch); // FIXME: This should not use the GMMU.
|
||||
map.DmaMapAddress = va;
|
||||
}
|
||||
else
|
||||
|
|
|
|||
Loading…
Reference in a new issue