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Remove CpuId IR instruction (#1227)

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gdkchan 2020-05-13 02:30:21 -03:00 committed by GitHub
parent 1f8e45c2ba
commit 96c7988671
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4 changed files with 0 additions and 44 deletions
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6
ARMeilleure/CodeGen/X86/CodeGenerator.cs
View file

@ -53,7 +53,6 @@ namespace ARMeilleure.CodeGen.X86
Add(Instruction.ConvertToFP, GenerateConvertToFP); Add(Instruction.ConvertToFP, GenerateConvertToFP);
Add(Instruction.Copy, GenerateCopy); Add(Instruction.Copy, GenerateCopy);
Add(Instruction.CountLeadingZeros, GenerateCountLeadingZeros); Add(Instruction.CountLeadingZeros, GenerateCountLeadingZeros);
Add(Instruction.CpuId, GenerateCpuId);
Add(Instruction.Divide, GenerateDivide); Add(Instruction.Divide, GenerateDivide);
Add(Instruction.DivideUI, GenerateDivideUI); Add(Instruction.DivideUI, GenerateDivideUI);
Add(Instruction.Fill, GenerateFill); Add(Instruction.Fill, GenerateFill);
@ -765,11 +764,6 @@ namespace ARMeilleure.CodeGen.X86
context.Assembler.Xor(dest, Const(operandMask), OperandType.I32); context.Assembler.Xor(dest, Const(operandMask), OperandType.I32);
} }
private static void GenerateCpuId(CodeGenContext context, Operation operation)
{
context.Assembler.Cpuid();
}
private static void GenerateDivide(CodeGenContext context, Operation operation) private static void GenerateDivide(CodeGenContext context, Operation operation)
{ {
Operand dest = operation.Destination; Operand dest = operation.Destination;

32
ARMeilleure/CodeGen/X86/PreAllocator.cs
View file

@ -265,38 +265,6 @@ namespace ARMeilleure.CodeGen.X86
break; break;
} }
case Instruction.CpuId:
{
// Handle the many restrictions of the CPU Id instruction:
// - EAX controls the information returned by this instruction.
// - When EAX is 1, feature information is returned.
// - The information is written to registers EAX, EBX, ECX and EDX.
Debug.Assert(dest.Type == OperandType.I64);
Operand eax = Gpr(X86Register.Rax, OperandType.I32);
Operand ebx = Gpr(X86Register.Rbx, OperandType.I32);
Operand ecx = Gpr(X86Register.Rcx, OperandType.I32);
Operand edx = Gpr(X86Register.Rdx, OperandType.I32);
// Value 0x01 = Version, family and feature information.
nodes.AddBefore(node, Operation(Instruction.Copy, eax, Const(1)));
// Copy results to the destination register.
// The values are split into 2 32-bits registers, we merge them
// into a single 64-bits register.
Operand rcx = Gpr(X86Register.Rcx, OperandType.I64);
node = nodes.AddAfter(node, Operation(Instruction.ZeroExtend32, dest, edx));
node = nodes.AddAfter(node, Operation(Instruction.ShiftLeft, dest, dest, Const(32)));
node = nodes.AddAfter(node, Operation(Instruction.BitwiseOr, dest, dest, rcx));
operation.SetDestinations(new Operand[] { eax, ebx, ecx, edx });
operation.SetSources(new Operand[] { eax });
break;
}
case Instruction.Divide: case Instruction.Divide:
case Instruction.DivideUI: case Instruction.DivideUI:
{ {

1
ARMeilleure/IntermediateRepresentation/Instruction.cs
View file

@ -69,7 +69,6 @@ namespace ARMeilleure.IntermediateRepresentation
ZeroExtend8, ZeroExtend8,
Clobber, Clobber,
CpuId,
Extended, Extended,
Fill, Fill,
LoadFromContext, LoadFromContext,

5
ARMeilleure/Translation/EmitterContext.cs
View file

@ -209,11 +209,6 @@ namespace ARMeilleure.Translation
return Add(Instruction.CountLeadingZeros, Local(op1.Type), op1); return Add(Instruction.CountLeadingZeros, Local(op1.Type), op1);
} }
internal Operand CpuId()
{
return Add(Instruction.CpuId, Local(OperandType.I64));
}
public Operand Divide(Operand op1, Operand op2) public Operand Divide(Operand op1, Operand op2)
{ {
return Add(Instruction.Divide, Local(op1.Type), op1, op2); return Add(Instruction.Divide, Local(op1.Type), op1, op2);