144 commits

Author	SHA1	Message	Date
LDj3SNuD	42e4e02a64	Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, Umlsl_V, Saddl_V, Ssubl_V, Usubl_V instructions; add 8 FP & 16 S/Umlal_V, S/Umlsl_V, S/Uaddl_V, S/Usubl_V Tests. (#390) ... * Update AOpCodeTable.cs * Update AInstEmitSimdCvt.cs * Update Pseudocode.cs * Update Instructions.cs * Update CpuTestSimd.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update Instructions.cs * Update CpuTestSimdReg.cs * Update CpuTestSimd.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update Instructions.cs * Update CpuTestSimdReg.cs * Add QCFlagBit. * Add QCFlagBit.	2018-09-01 11:52:51 -03:00
Merry	326777ca4a	Ryujinx.Tests: Add unicorn to test framework (#389) ... * Ryujinx.Tests: Add unicorn to test framework * CpuTestSimdArithmetic: Comment out inaccurate results	2018-09-01 11:24:05 -03:00