ff53dcf560
* dotnet format style --severity info Some changes were manually reverted. * dotnet format analyzers --serverity info Some changes have been minimally adapted. * Restore a few unused methods and variables * Silence dotnet format IDE0060 warnings * Silence dotnet format IDE0052 warnings * Address or silence dotnet format IDE1006 warnings * Address or silence dotnet format CA2208 warnings * Address dotnet format CA1822 warnings * Address or silence dotnet format CA1069 warnings * Silence CA1806 and CA1834 issues * Address dotnet format CA1401 warnings * Fix new dotnet-format issues after rebase * Address review comments * Address dotnet format CA2208 warnings properly * Fix formatting for switch expressions * Address most dotnet format whitespace warnings * Apply dotnet format whitespace formatting A few of them have been manually reverted and the corresponding warning was silenced * Add previously silenced warnings back I have no clue how these disappeared * Revert formatting changes for OpCodeTable.cs * Enable formatting for a few cases again * Format if-blocks correctly * Enable formatting for a few more cases again * Fix inline comment alignment * Run dotnet format after rebase and remove unused usings - analyzers - style - whitespace * Disable 'prefer switch expression' rule * Add comments to disabled warnings * Remove a few unused parameters * Adjust namespaces * Simplify properties and array initialization, Use const when possible, Remove trailing commas * Start working on disabled warnings * Fix and silence a few dotnet-format warnings again * Address IDE0251 warnings * Address a few disabled IDE0060 warnings * Silence IDE0060 in .editorconfig * Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas" This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e. * dotnet format whitespace after rebase * First dotnet format pass * Remove unnecessary formatting exclusion * Add unsafe dotnet format changes * Change visibility of JitSupportDarwin to internal
136 lines
4.4 KiB
C#
136 lines
4.4 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using static ARMeilleure.Instructions.InstEmitFlowHelper;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit32
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{
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public static void B(ArmEmitterContext context)
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{
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IOpCode32BImm op = (IOpCode32BImm)context.CurrOp;
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context.Branch(context.GetLabel((ulong)op.Immediate));
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}
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public static void Bl(ArmEmitterContext context)
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{
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Blx(context, x: false);
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}
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public static void Blx(ArmEmitterContext context)
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{
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Blx(context, x: true);
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}
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private static void Blx(ArmEmitterContext context, bool x)
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{
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IOpCode32BImm op = (IOpCode32BImm)context.CurrOp;
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uint pc = op.GetPc();
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bool isThumb = ((OpCode32)context.CurrOp).IsThumb;
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uint currentPc = isThumb
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? pc | 1
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: pc - 4;
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SetIntA32(context, GetBankedRegisterAlias(context.Mode, RegisterAlias.Aarch32Lr), Const(currentPc));
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// If x is true, then this is a branch with link and exchange.
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// In this case we need to swap the mode between Arm <-> Thumb.
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if (x)
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{
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SetFlag(context, PState.TFlag, Const(isThumb ? 0 : 1));
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}
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EmitCall(context, (ulong)op.Immediate);
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}
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public static void Blxr(ArmEmitterContext context)
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{
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IOpCode32BReg op = (IOpCode32BReg)context.CurrOp;
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uint pc = op.GetPc();
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Operand addr = context.Copy(GetIntA32(context, op.Rm));
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Operand bitOne = context.BitwiseAnd(addr, Const(1));
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bool isThumb = ((OpCode32)context.CurrOp).IsThumb;
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uint currentPc = isThumb
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? (pc - 2) | 1
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: pc - 4;
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SetIntA32(context, GetBankedRegisterAlias(context.Mode, RegisterAlias.Aarch32Lr), Const(currentPc));
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SetFlag(context, PState.TFlag, bitOne);
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EmitBxWritePc(context, addr);
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}
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public static void Bx(ArmEmitterContext context)
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{
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IOpCode32BReg op = (IOpCode32BReg)context.CurrOp;
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EmitBxWritePc(context, GetIntA32(context, op.Rm), op.Rm);
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}
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public static void Cbnz(ArmEmitterContext context) => EmitCb(context, onNotZero: true);
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public static void Cbz(ArmEmitterContext context) => EmitCb(context, onNotZero: false);
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private static void EmitCb(ArmEmitterContext context, bool onNotZero)
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{
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OpCodeT16BImmCmp op = (OpCodeT16BImmCmp)context.CurrOp;
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Operand value = GetIntA32(context, op.Rn);
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Operand lblTarget = context.GetLabel((ulong)op.Immediate);
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if (onNotZero)
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{
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context.BranchIfTrue(lblTarget, value);
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}
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else
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{
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context.BranchIfFalse(lblTarget, value);
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}
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}
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public static void It(ArmEmitterContext context)
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{
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OpCodeT16IfThen op = (OpCodeT16IfThen)context.CurrOp;
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context.SetIfThenBlockState(op.IfThenBlockConds);
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}
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public static void Tbb(ArmEmitterContext context) => EmitTb(context, halfword: false);
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public static void Tbh(ArmEmitterContext context) => EmitTb(context, halfword: true);
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private static void EmitTb(ArmEmitterContext context, bool halfword)
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{
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OpCodeT32Tb op = (OpCodeT32Tb)context.CurrOp;
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Operand halfwords;
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if (halfword)
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{
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Operand address = context.Add(GetIntA32(context, op.Rn), context.ShiftLeft(GetIntA32(context, op.Rm), Const(1)));
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halfwords = InstEmitMemoryHelper.EmitReadInt(context, address, 1);
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}
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else
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{
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Operand address = context.Add(GetIntA32(context, op.Rn), GetIntA32(context, op.Rm));
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halfwords = InstEmitMemoryHelper.EmitReadIntAligned(context, address, 0);
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}
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Operand targetAddress = context.Add(Const((int)op.GetPc()), context.ShiftLeft(halfwords, Const(1)));
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EmitVirtualJump(context, targetAddress, isReturn: false);
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}
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}
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}
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