Ryujinx/ARMeilleure/CodeGen/X86
2022-08-14 17:35:08 -03:00
..
Assembler.cs Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015) 2022-01-21 12:47:34 -03:00
AssemblerTable.cs PreAllocator: Check if instruction supports a Vex prefix in IsVexSameOperandDestSrc1 (#3587) 2022-08-14 17:35:08 -03:00
CallConvName.cs Add a new JIT compiler for CPU code (#693) 2019-08-08 21:56:22 +03:00
CallingConvention.cs misc: Migrate usage of RuntimeInformation to OperatingSystem (#2901) 2021-12-04 20:02:30 -03:00
CodeGenCommon.cs Optimize x64 loads and stores using complex addressing modes (#972) 2020-03-10 09:29:34 +11:00
CodeGenContext.cs Add Operand.Label support to Assembler (#2680) 2021-10-05 14:04:55 -03:00
CodeGenerator.cs Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015) 2022-01-21 12:47:34 -03:00
HardwareCapabilities.cs CPU (A64): Add FP16/FP32 fast paths (F16C Intrinsics) for Fcvt_S, Fcvtl_V & Fcvtn_V Instructions. Now HardwareCapabilities uses CpuId. (#1650) 2020-11-18 19:35:54 +01:00
IntrinsicInfo.cs Add a new JIT compiler for CPU code (#693) 2019-08-08 21:56:22 +03:00
IntrinsicTable.cs CPU (A64): Add Fmaxnmp & Fminnmp Scalar Inst.s, Fast & Slow Paths; with Tests. (#1894) 2021-01-20 09:12:33 +11:00
IntrinsicType.cs Add support for guest Fz (Fpcr) mode through host Ftz and Daz (Mxcsr) modes (fast paths). (#1630) 2020-12-07 10:37:07 +01:00
PreAllocator.cs PreAllocator: Check if instruction supports a Vex prefix in IsVexSameOperandDestSrc1 (#3587) 2022-08-14 17:35:08 -03:00
X86Condition.cs Improve branch operations (#1442) 2020-08-05 08:52:33 +10:00
X86Instruction.cs Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow paths (using fused inst.s). Fix Vfma_V slow path not using StandardFPSCRValue(). (#1775) 2020-12-17 20:43:41 +01:00
X86Optimizer.cs Add a limit on the number of uses a constant may have (#3097) 2022-02-09 17:42:47 -03:00
X86Register.cs Add a new JIT compiler for CPU code (#693) 2019-08-08 21:56:22 +03:00